Display devices such as CRT's or LCD's are widely used to display full motion, or live, video images. Display devices are often used to display only a single video image at any one time. However, there are also ways of allowing more than one, or multiple, full motion video images to be simultaneously displayed on a signal display device. Such multiple video images are typically displayed in separate "windows" on the display device. FIG. 1 illustrates a display device 900 on which a single video window 910 is displayed. FIG. 2 illustrates a display device 900 on which multiple video windows 920 are displayed.
The currently known techniques for accomplishing the simultaneous display of multiple video images on a single display device do, however, have certain disadvantages associated with it. In short, these disadvantages include high cost, and the need for complex circuitry.
One common technique of accomplishing the simultaneous display of multiple live video images on a signal display device is illustrated in FIG. 3. With this technique, video signals A, B and C, which represent separate video images, are input to and processed individually via separate video interface circuitry 310, 320, and 330. The video interface circuitry 310, 320, and 330 digitizes and extracts timing information for each video signal A, B and C, respectively. The video interface circuit may also be used to perform other processing operations, such as adjusting the size of the digitized video image. The resulting digital data for each video image is then output to a respective separate video buffer memory 350, 360 or 370 where it is temporarily stored before being output to a main interface circuit 380. The main interface circuit 380 converts the digital data output by the buffer memories into an analog signal and adds appropriate timing information. Further, the outputs of all of the buffer memories 350, 360 and 370 are combined by, and output to monitor 390 through, the main interface circuit 380. The addressing and output of all buffer memories 350, 360 and 370 is controlled by a clock/control circuit 340. The contents of the buffer memories 350, 360 and 370 are simultaneously read out at a rate which is substantially equal to the rate at which pixel information is being displayed on display monitor 390. The output of each buffer memory 350, 360 and 370 is controlled so that information stored in each address location in the buffer memory is output at an appropriate time to produce a visual image on monitor 390 which corresponds to data stored in each buffer memory 350, 360 and 370 as combined by interface circuit 380. One disadvantage of this technique of displaying multiple video images is that it requires complex and expensive memory and control circuitry and does not perform well as the number of live video image signals which are input increases.
Another common technique is shown in FIG. 4. Here multiple video signals D,E and F, which represent separate full motion images are input to and processed by separate video interface circuits 410, 420 or 430 respectively. All of the resulting processed video data output from each interface circuit are then combined, or multiplexed, and temporarily stored in a single buffer memory 450. Clock control circuit 440 controls the output of each video interface circuit 410, 420 and 430 to buffer memory 450, and also generates memory addressing information for the video data output from each of the video interface circuits and stored in buffer memory 450. This video data is then output or read out of buffer memory into interface circuit 380 wherein is processed and output as a signal Z appropriate for driving monitor 390 to display imagery and information represented by signal Z. While this technique requires less buffer memory than the technique shown in FIG. 3, it has several disadvantages. First, each of the video interfaces 410, 420 and 430 generate a constant stream of data which must be written into the buffer memory. This requires a very high data bandwidth which means that expensive high performance buffer memories must be used. Secondly, as the number of video signals which are desired to be input increases, the performance requirements, such as speed or bandwidth of the buffer memory increases. In addition, where overlapping live video windows are desired, additional complicated circuitry for addressing and control functions must be used. Further, in situations where cost constraints require the use of a single, low-performance buffer memory, the data bandwidth of the live video signal or stream must be reduced by either reducing the resolution of the displayed video images or decreasing the size of the video image to be displayed.
Another apparatus for accomplishing the display of multiple live video images is illustrated in FIG. 5. Here, all of the input video signals G, H and I are multiplexed via video select multiplexer 560 and output to one video interface 5 10. Assuming that all of the input video signals G, H and I are synchronous, the clock/control circuitry 520 will select a new or different input video signal G, H or I during the video blanking interval between successive frames. In this manner, the maximum total data rate can be maintained constant regardless of the number of input video signals. However, as the number of input video signals increases, the display update rate (the rate at which new display information is provided to the display device) of the video signals will be decreased due to the additional time which will be required to access/select the additional input video signals for input to video interface 510.